ASIC Chips : Things You Should Know

Printed circuit boards (PCBs) were used for implementing specific system requirements till a few decades ago. Printed circuit boards occupied more space and system breakdowns were frequent. Fast progress in microelectronics totally changed this approach. Systems, which required printed circuit boards, are now being put together in a single chip. Such systems-on-a-chip (SOCs) have become a reality because of vast improvements in chip fabrication and processing technologies. The most important component in an SOC and similar other semi-conductor chips are Application Specific Integrated Circuits (ASICs).

ASIC chips

The ASIC chips are circuit blocks specifically designed for a particular application or an application domain. In some other applications, ASICs are put together in a separate chip. Electronic circuits used in modern gadgets combine many functions into a single circuit. Consider the recent versions of desktops and laptops. Manufacturers are increasingly focusing on miniaturization and adding more functions. For instance, an audio decoder circuit is now being implemented as an ASIC chip in the motherboards of desktops and laptops instead of using a separate device for the particular application. Other multi-media devices also follow the same procedure. The custom nature of the ASIC chip design has made it possible to squeeze in more functionality under specific system size, while simultaneously reducing power requirements, heat and cost. This would not have been a possibility if standard IC (Integrated chip) parts were used. Due to cost and performance advantages, ASICs and semi-conductor chips with ASIC blocks are now used in a wide range of products from consumer electronics to space applications.

Main Benefits

The main advantage of an ASIC chip is that it reduces the requirement for a large number of devices and thus requires less board space. When large numbers of components are integrated into a single chip, it reduces component cost and manufacturing cost while simultaneously improving the reliability and manufacturing process of the chip. The use of computer-aided design (CAD) techniques to design the chip helps to integrate complex circuits into a single chip.

The Procedure

The ASIC design process consists of defining circuit inputs and outputs, hand calculations, circuit simulations, layout of the circuit, simulations including parasitic, re-evaluation of circuit inputs and outputs, fabrication and testing. Parasitics are the stray capacitances, inductances, pn junctions and bipolar transistors associated with problems like frequent breakdowns, stored charges, latch-ups etc. The circuit specifications during the design phase are rarely set in concrete terms. They may change as the project matures. This can be the result of tradeoffs made between cost and performance, changes in the marketability of the chip, or simply changes in the customer's needs. In almost all cases, a major change in an ASIC chip after it has gone into production is not possible.

Programming of ASIC chip

The functions in an ASIC chip are programmed using hardware description languages (HDLs) like Verilog or VHDL (Very High Speed Integrated Circuit Hardware Description Language). Since feature sizes are shrinking and improved design tools are available the number of gates incorporated into an ASIC has increased from a few thousands to several millions. Verilog is mainly used for programming electronic systems. It supports the design, verification and implementation of analog, digital and mixed-signal circuits at various levels of abstraction. The syntax of Verilog is very similar to that of the C language, even though there are some differences. The VHDL is mostly used as a design-entry language for ASICs, especially in the design of digital circuits. The main advantage of VHDL is that it allows the main functions of the required system to be modelled and simulated before the design is translated into real hardware.

Testing of Chip

The ASIC chip is so complex that the cost involved in testing and producing the chip is almost the same. ASIC chip manufacturers earlier spent two-thirds of their time in designing a chip. Now they are forced to spend almost the same amount of time in running simulations to see that the design will work. Recent trends include using the built-in self-test (BIST) and the design-for-test (DFT) processes to reduce costs. Some design companies even refer the BIST to other companies. The BIST mechanism verifies the internal functionality of the chip The main purpose of BIST is to reduce the complexity of the circuit and thus reduce the cost by reducing test-cycle duration and the complexity of test/probe set-up. The DFT method is applied during chip manufacturing and also for hardware maintenance. Such tests normally include test programs that execute in Automatic Test Equipment (ATE) environments. A test failure indicates the presence of defects. When chips fail during test then the information for the failure is collected into a fail log. The fail log will give information as to when (in which tester cycle), where (at what tester channel) and how (at which logic value) the test failed.

Methods for Chip production

The chip production process involves register-transfer level (RTL) description, simulation, synthesis, extraction and physical verification. The programmable interconnects allow the logic blocks to be interconnected by an expert. The 45-nanometer (nm) semiconductor manufacturing process uses the "wet" lithography process to double the number of chips produced on each silicon wafer. This method improves processing performance by 30 percent and reduces power consumption by 40 percent. Further research is going on to adopt newer techniques to enhance performance and reduce cost through the use of dual work function metal gates in the 45-nm roadmap using either the full-silicidation-of-polysilicon (FuSI) or a combination of metal plus a silicide. Using metal gates made from silicon nitride dielectrics, power consumption can be reduced and the use of complex high-k materials, which are costly, can be avoided. The popular gate array manufacturing method follows a process in which the diffused layers consisting of transistors and other devices are predefined and wafers containing those devices are held in place prior to metallisation. The interconnections in the final device are determined using the physical design process. It involves two to five metal layers, with each metal layer running perpendicular to the one just below it. These metal layers require photo-lithographic masks. Since metallisation is a quick process, the production cycles are shorter.