Electronics Tutorial: The JK Flip Flop

This article assumes the reader has a knowledge of the basic building blocks of digital circuits. It covers the operation of the JK Flip Flop.

The truth table for the JK Flip Flop is shown in Figure one. Note that the truth table is similar to other flip flops except when both the J input and the K inputs are high. A JK Flip Flop is also shown in figure one. It has two inputs J and K and a clock to synchronize it's operation. It's outputs are Q and QN. The outputs Q and QN are always in opposite states. If Q is high then QN is low and visa versa.

When the inputs J and K are low, the outputs Q and QN remain in their previous states; they do not change. When the input J is low and the input K is high, the output Q goes low and the output QN goes high. When the input J is high and the input K is low, the output Q goes high and the output QN goes low. When the input J is high and the input K is high, the outputs Q and QN switch states with each clock pulse.

The JK Flip Flop circuit is shown in figure two. The inputs J and K must be stable during the positive clock pulses. The unused gate inputs must not be left floating. They must be connected to another input, a power supply or ground. The inputs of A1 and A3 are propagated to the outputs during the positive pulse of the clock. During the negative half of the clock cycle, the outputs of A1 and A3 are high causing the outputs Q and QN to remains in their previous states. The positive pulse of the clock must have a shorter duration than the time it takes for the inputs (J and K) of the flip flop to propagate to the outputs (Q and QN).

The waveforms are shown in figure three. There are five waveforms shown. Note that the clock is the top waveform. Each period of the clock is labeled t1, t2, t3, etc. Each clock period covers one complete cycle of the clock.

The initial states of the inputs and outputs are shown in the column labeled t1. Note that the state of inputs J and K during the positive pulse of the clock is not shown in the clock period labeled t1. The input J is at a logic high. The input K is at a logic low. The outputs Q and QN will not respond to these inputs until the next positive clock pulse. Hence, the output Q is low and the output QN is high.

During the period t2, the output Q goes high and the output QN goes low. These outputs are responding to the states of the inputs J and K during the clock period t2. The inputs J and K must be stable just prior to and during the positive clock pulse.

During the period t3, the states of the J and K inputs change. The change in the J and K inputs occur after the positive pulse of the clock during t3. The J input goes low and the K input goes high. The response to the changed inputs happen during the positive clock pulse during the clock period t4. The output Q goes low and the output QN goes high.

Look at the clock period t6. Both the J input and the K input are high. On the positive clock pulse, the state of both outputs Q and QN change. For the clock periods t7, t8 and t9, both inputs J and K remain high during the positive clock pulse. The outputs Q and QN change during each clock period t7, t8 and t9. Hence the outputs Q and QN "toggle" with each clock cycle. Also note that the frequency of the Q and QN outputs is exactly half the frequency of the clock.

After the T9 positive clock pulse, the K input goes low. During the t10 clock pulse, the Q output goes high and the QN output goes low. The inputs and outputs remain the same for the t11 clock period.

References:
I have a Bachelor of Science in Electrical Engineering and worked as an electronics tecchnician.

Digital Circuits and Microprocessors
Herbert Taub
ISBN 0-07-062945-5